1. Field of the Invention
The invention relates to an integrated circuit structure, and particularly relates to a multi-die stack structure.
2. Description of Related Art
Multi-die stack structures are often applied to electronic products that require increased memory density and/or device performance in a reduced package size.
FIG. 1 illustrates a conventional multi-die stack structure of QDP (quad-die package) type with a “ladder-style” connection between the dies that is based on CS (Chip-Select) pads. Such a structure is currently applied to DDR3 SDRAM (Double-Data-Rate Three Synchronous Dynamic Random Access Memory).
Referring to FIG. 1, the structure includes four dies 12, 14, 16 and 18 vertically stacked from bottom to top. Each die 12, 14, 16 or 18 has four CS pads including a CS0 pad 101 for the input of the die, a CS1 pad 103 for the input of the 1-level higher die (if present), a CS2 pad 105 for the input of the 2-level higher die (if present), and a CS3 pad 107 for the input of the 4-level higher die (if present), wherein the CS pads 101, 103, 105 and 107 of the dies 12, 14, 16 and 18 are connected in a “ladder style” via through-substrate via (TSV). More specifically, in each ith die (i=2 to 4) 14, 16 or 18, the jth pad (j=1 to 3) 101, 103 or 105 is electrically connected with the (j+k)-th pad of each (i−k)-th die (k=1 to i−1), with a proviso of j+k≦4.
However, the ladder-style connection in DDR3 SDRAM suffers from large input-capacitance (Cin) difference between the CS/ZQ pads. This can most likely be attributed to the loading difference seen by the respective CS pads. As shown in FIG. 1, the CS0 pad 101 has 0-TSV/1-pad loading, the CS1 pad 103 has 1-TSV/2-pad loading, the CS2 pad 105 has 2-TSV/3-pad loading, and the CS3 pad 105 has 3-TSV/4-pad loading. That is, a CS(n+1) pad has an extra 1-TSV/1-pad loading as compared to a CS(n) pad.